Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/66904
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Title: A 3.0 gb/s throughput hardware-efficient decoder for cyclically-coupled QC-LDPC codes
Authors: Lu, Q
Fan, JF
Sham, CW
Tam, WM
Lau, FCM 
Issue Date: Jan-2016
Source: IEEE transactions on circuits and systems. I, Regular papers, Jan. 2016, v. 63, no. 1, p. 134-145
Keywords: Cyclically-coupled QC-LDPC code
Decoder architecture
FPGA implementation
QC-LDPC code
Publisher: Institute of Electrical and Electronics Engineers
Journal: IEEE transactions on circuits and systems. I, Regular papers 
ISSN: 1549-8328
EISSN: 1558-0806
DOI: 10.1109/TCSI.2015.2510619
Rights: © 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
The following publication Q. Lu, J. Fan, C. Sham, W. M. Tam and F. C. M. Lau, "A 3.0 Gb/s Throughput Hardware-Efficient Decoder for Cyclically-Coupled QC-LDPC Codes," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 63, no. 1, pp. 134-145, Jan. 2016 is available at https://dx.doi.org/10.1109/TCSI.2015.2510619.
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