Device physics and architecture advances in tunnel field-effect transistors

Abstract

The persistent pursuit of miniaturization and energy efficiency in semiconductor technology has driven the scaling of complementary metal-oxide-semiconductor field-effect transistors (CMOS FETs, i.e., the MOSFETs) to their physical limits. Conventional MOSFETs face intrinsic challenges, especially the Boltzmann limit that imposes a fundamental lower bound on the subthreshold swing (SS ≥ 60 mV dec−1 at room temperature). This limitation severely restricts voltage scaling and exacerbates static power dissipation. To overcome these bottlenecks, tunnel field-effect transistors (TFETs) have emerged as a promising post-CMOS alternative. The advantages of ultra-small SS well below the Boltzmann limit, as well as ultralow leakage currents, make TFETs ideal for low-power electronics and energy-efficient computing in the future information industry. However, its current development has encountered significant resistance to further performance improvement requirements; new breakthroughs have evolved to be based on interdisciplinary research that covers materials science, device technology, theoretical physics, and so on. Here, we provide a review on the design and development of TFET, which mainly describes the device physics model of tunnel junctions, and discusses the optimization direction of key parameters, the design direction of potential structures, and the development direction of the innovation system based on the device physics. Also, we visualize the framework for the figures of merit of TFET performance and further forecast the future applications of TFET.