Doped low-density parity-check codes

Abstract

In this paper, we propose a doping approach to lower the error floor of Low-Density Parity-Check (LDPC) codes. The doping component is a short block code in which the information bits are selected from the coded bits of the dominant trapping sets of the LDPC code. Accordingly, an algorithm for selecting the information bits of the short code is proposed, and a specific two-stage decoding algorithm is presented. Simulation results demonstrate that the proposed doped LDPC code achieves up to 2.0 ​dB gain compared with the original LDPC code at a frame error rate of 10−6. Furthermore, the proposed design can lower the error floor of original LDPC codes.