Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/100315
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dc.contributorDepartment of Applied Physicsen_US
dc.creatorWang, Jen_US
dc.creatorGuo, Xen_US
dc.creatorYu, Zen_US
dc.creatorMa, Zen_US
dc.creatorLiu, Yen_US
dc.creatorChan, Men_US
dc.creatorZhu, Yen_US
dc.creatorWang, Xen_US
dc.creatorChai, Yen_US
dc.date.accessioned2023-08-08T01:54:56Z-
dc.date.available2023-08-08T01:54:56Z-
dc.identifier.isbn978-1-7281-1987-8 (Electronic)en_US
dc.identifier.isbn978-1-7281-1988-5 (Print on Demand(PoD))en_US
dc.identifier.urihttp://hdl.handle.net/10397/100315-
dc.language.isoenen_US
dc.publisherIEEEen_US
dc.rights© 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.en_US
dc.rightsThe following publication J. Wang et al., "Steep Slope p-type 2D WSe2 Field-Effect Transistors with Van Der Waals Contact and Negative Capacitance," 2018 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2018, pp. 22.3.1-22.3.4 is available at https://doi.org/10.1109/IEDM.2018.8614493.en_US
dc.titleSteep slope p-type 2D WSe 2 field-effect transistors with van der waals contact and negative capacitanceen_US
dc.typeConference Paperen_US
dc.identifier.spage22.3.1en_US
dc.identifier.epage22.3.4en_US
dc.identifier.doi10.1109/IEDM.2018.8614493en_US
dcterms.abstractSteep-slope p-type 2D WSe 2 back-gated field-effect transistors (FETs) are realized by using van der Waals Pt-WSe 2 contact and HfZrO 2 / Al 2 O 3 as the dielectric layer. The van der Waals Pt-WSe 2 contact is free from disorder and Fermi level pinning and decreases the subthreshold slope. The WSe 2 NCFET with van der Waals contact shows low subthreshold slope for both forward and reverse gate voltage sweep (the minimum SS forward =18.2 mV dec and SS reverse =44.1 mV dec) with a hysteresis as small as 20 mV at subthreshold region.en_US
dcterms.accessRightsopen accessen_US
dcterms.bibliographicCitation2018 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA , 1-5 Dec. 2018, p. 1-4en_US
dcterms.issued2018-
dc.identifier.scopus2-s2.0-85061838419-
dc.relation.ispartofbook2018 IEEE International Electron Devices Meeting (IEDM)en_US
dc.relation.conferenceIEEE International Electron Devices Meeting [IEDM]en_US
dc.description.validate202308 bcvcen_US
dc.description.oaAccepted Manuscripten_US
dc.identifier.FolderNumberAP-0388-
dc.description.fundingSourceRGCen_US
dc.description.fundingSourceOthersen_US
dc.description.fundingTextNational Natural Science Foundation of Chinaen_US
dc.description.pubStatusPublisheden_US
dc.identifier.OPUS13158032-
dc.description.oaCategoryGreen (AAM)en_US
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