Please use this identifier to cite or link to this item:
http://hdl.handle.net/10397/93904
DC Field | Value | Language |
---|---|---|
dc.contributor | Department of Applied Mathematics | - |
dc.creator | Yiu, KFC | en_US |
dc.date.accessioned | 2022-08-03T01:24:09Z | - |
dc.date.available | 2022-08-03T01:24:09Z | - |
dc.identifier.issn | 1380-7501 | en_US |
dc.identifier.uri | http://hdl.handle.net/10397/93904 | - |
dc.language.iso | en | en_US |
dc.publisher | Springer | en_US |
dc.rights | © Springer Science+Business Media, LLC, part of Springer Nature 2019 | en_US |
dc.rights | This version of the article has been accepted for publication, after peer review (when applicable) and is subject to Springer Nature’s AM terms of use (https://www.springernature.com/gp/open-research/policies/accepted-manuscript-terms), but is not the Version of Record and does not reflect post-acceptance improvements, or any corrections. The Version of Record is available online at: http://dx.doi.org/10.1007/s11042-019-7590-8 | en_US |
dc.subject | Beamforming | en_US |
dc.subject | FPGA | en_US |
dc.subject | Signal enhancement | en_US |
dc.title | A parallel beamforming system with real-time implementation | en_US |
dc.type | Journal/Magazine Article | en_US |
dc.identifier.spage | 23581 | en_US |
dc.identifier.epage | 23595 | en_US |
dc.identifier.volume | 78 | en_US |
dc.identifier.issue | 16 | en_US |
dc.identifier.doi | 10.1007/s11042-019-7590-8 | en_US |
dcterms.abstract | For voice control applications, it is common to employ a microphone array to enhance received signals via beamforming techniques. In designing beamformers, different criteria will lead to different signal performance. It is known that speech recognition accuracy relies heavily on the trade-off between signal distortion and noise reduction. In this paper, we propose a novel beamformer structure which can give a continuous profile in signal distortion and noise reduction. The proposed structure combines two existing optimal beamformers to form the final filter. Moreover, since both optimal beamforming filters can be executed in parallel, a method is proposed to implement the noise reduction algorithm in the frequency domain. By studying the accuracy and efficiency of different modules, a hybrid fixed-floating point arithmetic is proposed within an FPGA hardware architecture to form an embedded system for industrial applications. | - |
dcterms.accessRights | open access | en_US |
dcterms.bibliographicCitation | Multimedia tools and applications, Aug. 2019, v. 78, no. 16, p. 23581-23595 | en_US |
dcterms.isPartOf | Multimedia tools and applications | en_US |
dcterms.issued | 2019-08 | - |
dc.identifier.scopus | 2-s2.0-85065538822 | - |
dc.description.validate | 202208 bcfc | - |
dc.description.oa | Accepted Manuscript | en_US |
dc.identifier.FolderNumber | AMA-0266 | - |
dc.description.fundingSource | RGC | en_US |
dc.description.fundingSource | Others | en_US |
dc.description.fundingText | PolyU | en_US |
dc.description.pubStatus | Published | en_US |
dc.identifier.OPUS | 14561344 | - |
Appears in Collections: | Journal/Magazine Article |
Files in This Item:
File | Description | Size | Format | |
---|---|---|---|---|
Yiu_Parallel_Beamforming_System.pdf | Pre-Published version | 1 MB | Adobe PDF | View/Open |
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