Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/68455
Title: High throughput decoder architecture for low-density parity-check convolutional codes
Authors: Sham, CW 
Chen, X 
Lau, CM 
Zhao, Y 
Tam, WM 
Issue Date: 11-Mar-2014
Source: US Patent 8,671,323 B2. Washington, DC: US Patent and Trademark Office, 2014. How to cite?
Abstract: A Low-Density Parity-Check Convolutional Code (LPDCCC) decoder (10) for partial parallel decoding of low-density parity-check convolutional codes, the decoder having: a plurality of pipeline processors (11) to receive channel messages and edge-messages; each processor (11) having: a plurality of block processing units (BPUs) (13), each BPU (13) having a plurality of check node processors (CNPs) (14) to process check nodes that enter into the processor (11) and a plurality of variable node processors (VNPs) (15) to process variable nodes that are about to leave the processor (11); and a plurality of Random Access Memory (RAM) blocks (30) for dynamic message storage of the channel messages and the edge-messages; wherein in each processor (11), the VNPs (15) are directly connected to corresponding RAM blocks (30), and the CNPs (14) are directly connected to corresponding RAM blocks (30) such that the connections from the VNPs (15) and CNPs (14) to the corresponding RAM blocks (30) are pre-defined and fixed according to a parity-check matrix of an unterminated time-varying periodic LDPCCC.
URI: http://hdl.handle.net/10397/68455
Rights: Assignee: The Hong Kong Polytechnic Univeristy.
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