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dc.contributor.authorSham, CWen_US
dc.contributor.authorChen, Xen_US
dc.contributor.authorLau, CMen_US
dc.contributor.authorZhao, Yen_US
dc.contributor.authorTam, WMen_US
dc.identifier.citationUS Patent 8,671,323 B2. Washington, DC: US Patent and Trademark Office, 2014.en_US
dc.description.abstractA Low-Density Parity-Check Convolutional Code (LPDCCC) decoder (10) for partial parallel decoding of low-density parity-check convolutional codes, the decoder having: a plurality of pipeline processors (11) to receive channel messages and edge-messages; each processor (11) having: a plurality of block processing units (BPUs) (13), each BPU (13) having a plurality of check node processors (CNPs) (14) to process check nodes that enter into the processor (11) and a plurality of variable node processors (VNPs) (15) to process variable nodes that are about to leave the processor (11); and a plurality of Random Access Memory (RAM) blocks (30) for dynamic message storage of the channel messages and the edge-messages; wherein in each processor (11), the VNPs (15) are directly connected to corresponding RAM blocks (30), and the CNPs (14) are directly connected to corresponding RAM blocks (30) such that the connections from the VNPs (15) and CNPs (14) to the corresponding RAM blocks (30) are pre-defined and fixed according to a parity-check matrix of an unterminated time-varying periodic LDPCCC.en_US
dc.description.sponsorshipDepartment of Electronic and Information Engineeringen_US
dc.rightsAssignee: The Hong Kong Polytechnic Univeristy.en_US
dc.titleHigh throughput decoder architecture for low-density parity-check convolutional codesen_US
dc.description.otherinformationUS8671323; US8671323 B2; US8671323B2; US8,671,323; US 8,671,323 B2; 8671323; Appl. No. 13/371,067en_US
dc.description.ros2013-2014 > Other Outputs > Patents granted-
Appears in Collections:Patent
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