Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/27392
Title: A 2.0 Gb/s throughput decoder for QC-LDPC convolutional codes
Authors: Sham, CW
Chen, X
Lau, FCM 
Zhao, Y
Tam, WM
Keywords: Decoder architecture
FPGA implementation
LDPC convolutional code
QC-LDPC convolutional code
Issue Date: 2013
Publisher: Institute of Electrical and Electronics Engineers
Source: IEEE transactions on circuits and systems. I, Regular papers, 2013, v. 60, no. 7, 6481477, p. 1857-1869 How to cite?
Journal: IEEE transactions on circuits and systems. I, Regular papers 
Abstract: This paper proposes a decoder architecture for low-density parity-check convolutional code (LDPCCC). Specifically, the LDPCCC is derived from a quasi-cyclic (QC) LDPC block code. By making use of the quasi-cyclic structure, the proposed LDPCCC decoder adopts a dynamic message storage in the memory and uses a simple address controller. The decoder efficiently combines the memories in the pipelining processors into a large memory block so as to take advantage of the data-width of the embedded memory in a modern field-programmable gate array (FPGA). A rate-5/6 QC-LDPCCC has been implemented on an Altera Stratix FPGA. It achieves up to 2.0 Gb/s throughput with a clock frequency of 100 MHz. Moreover, the decoder displays an excellent error performance of lower than 10-13 at a bit-energy-to-noise power-spectral-density ratio (E b/N0) of 3.55 dB.
URI: http://hdl.handle.net/10397/27392
ISSN: 1549-8328
EISSN: 1558-0806
DOI: 10.1109/TCSI.2012.2230506
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