Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/27392
PIRA download icon_1.1View/Download Full Text
Title: A 2.0 Gb/s throughput decoder for QC-LDPC convolutional codes
Authors: Sham, CW
Chen, X
Lau, FCM 
Zhao, Y
Tam, WM
Issue Date: Jul-2013
Source: IEEE transactions on circuits and systems. I, Regular papers, July 2013, v. 60, no. 7, 6481477, p. 1857-1869
Abstract: This paper proposes a decoder architecture for low-density parity-check convolutional code (LDPCCC). Specifically, the LDPCCC is derived from a quasi-cyclic (QC) LDPC block code. By making use of the quasi-cyclic structure, the proposed LDPCCC decoder adopts a dynamic message storage in the memory and uses a simple address controller. The decoder efficiently combines the memories in the pipelining processors into a large memory block so as to take advantage of the data-width of the embedded memory in a modern field-programmable gate array (FPGA). A rate-5/6 QC-LDPCCC has been implemented on an Altera Stratix FPGA. It achieves up to 2.0 Gb/s throughput with a clock frequency of 100 MHz. Moreover, the decoder displays an excellent error performance of lower than 10-13 at a bit-energy-to-noise power-spectral-density ratio (E b/N0) of 3.55 dB.
Keywords: Decoder architecture
FPGA implementation
LDPC convolutional code
QC-LDPC convolutional code
Publisher: Institute of Electrical and Electronics Engineers
Journal: IEEE transactions on circuits and systems. I, Regular papers 
ISSN: 1549-8328
EISSN: 1558-0806
DOI: 10.1109/TCSI.2012.2230506
Rights: © 2013 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
The following publication C. Sham, X. Chen, F. C. M. Lau, Y. Zhao and W. M. Tam, "A 2.0 Gb/s Throughput Decoder for QC-LDPC Convolutional Codes," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 60, no. 7, pp. 1857-1869, July 2013 is available at https://dx.doi.org/10.1109/TCSI.2012.2230506.
Appears in Collections:Journal/Magazine Article

Files in This Item:
File Description SizeFormat 
a0721-n10_2013_TCAS1.pdfPre-Published version1.4 MBAdobe PDFView/Open
Open Access Information
Status open access
File Version Final Accepted Manuscript
Access
View full-text via PolyU eLinks SFX Query
Show full item record

Page views

143
Last Week
0
Last month
Citations as of Mar 17, 2024

Downloads

47
Citations as of Mar 17, 2024

SCOPUSTM   
Citations

40
Last Week
1
Last month
0
Citations as of Mar 15, 2024

WEB OF SCIENCETM
Citations

34
Last Week
1
Last month
1
Citations as of Mar 14, 2024

Google ScholarTM

Check

Altmetric


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.