Please use this identifier to cite or link to this item:
http://hdl.handle.net/10397/27392
DC Field | Value | Language |
---|---|---|
dc.contributor | Department of Electronic and Information Engineering | en_US |
dc.creator | Sham, CW | en_US |
dc.creator | Chen, X | en_US |
dc.creator | Lau, FCM | en_US |
dc.creator | Zhao, Y | en_US |
dc.creator | Tam, WM | en_US |
dc.date.accessioned | 2015-05-26T08:17:01Z | - |
dc.date.available | 2015-05-26T08:17:01Z | - |
dc.identifier.issn | 1549-8328 | en_US |
dc.identifier.uri | http://hdl.handle.net/10397/27392 | - |
dc.language.iso | en | en_US |
dc.publisher | Institute of Electrical and Electronics Engineers | en_US |
dc.rights | © 2013 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. | en_US |
dc.rights | The following publication C. Sham, X. Chen, F. C. M. Lau, Y. Zhao and W. M. Tam, "A 2.0 Gb/s Throughput Decoder for QC-LDPC Convolutional Codes," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 60, no. 7, pp. 1857-1869, July 2013 is available at https://dx.doi.org/10.1109/TCSI.2012.2230506. | en_US |
dc.subject | Decoder architecture | en_US |
dc.subject | FPGA implementation | en_US |
dc.subject | LDPC convolutional code | en_US |
dc.subject | QC-LDPC convolutional code | en_US |
dc.title | A 2.0 Gb/s throughput decoder for QC-LDPC convolutional codes | en_US |
dc.type | Journal/Magazine Article | en_US |
dc.identifier.spage | 1857 | en_US |
dc.identifier.epage | 1869 | en_US |
dc.identifier.volume | 60 | en_US |
dc.identifier.issue | 7 | en_US |
dc.identifier.doi | 10.1109/TCSI.2012.2230506 | en_US |
dcterms.abstract | This paper proposes a decoder architecture for low-density parity-check convolutional code (LDPCCC). Specifically, the LDPCCC is derived from a quasi-cyclic (QC) LDPC block code. By making use of the quasi-cyclic structure, the proposed LDPCCC decoder adopts a dynamic message storage in the memory and uses a simple address controller. The decoder efficiently combines the memories in the pipelining processors into a large memory block so as to take advantage of the data-width of the embedded memory in a modern field-programmable gate array (FPGA). A rate-5/6 QC-LDPCCC has been implemented on an Altera Stratix FPGA. It achieves up to 2.0 Gb/s throughput with a clock frequency of 100 MHz. Moreover, the decoder displays an excellent error performance of lower than 10-13 at a bit-energy-to-noise power-spectral-density ratio (E b/N0) of 3.55 dB. | en_US |
dcterms.accessRights | open access | en_US |
dcterms.bibliographicCitation | IEEE transactions on circuits and systems. I, Regular papers, July 2013, v. 60, no. 7, 6481477, p. 1857-1869 | en_US |
dcterms.isPartOf | IEEE transactions on circuits and systems. I, Regular papers | en_US |
dcterms.issued | 2013-07 | - |
dc.identifier.isi | WOS:000322331200015 | - |
dc.identifier.scopus | 2-s2.0-84880052598 | - |
dc.identifier.eissn | 1558-0806 | en_US |
dc.identifier.rosgroupid | r69421 | - |
dc.description.ros | 2013-2014 > Academic research: refereed > Publication in refereed journal | en_US |
dc.description.oa | Accepted Manuscript | en_US |
dc.identifier.FolderNumber | a0721-n10 | - |
dc.description.fundingSource | RGC | en_US |
dc.description.fundingText | RGC: 519011E | en_US |
dc.description.pubStatus | Published | en_US |
Appears in Collections: | Journal/Magazine Article |
Files in This Item:
File | Description | Size | Format | |
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a0721-n10_2013_TCAS1.pdf | Pre-Published version | 1.4 MB | Adobe PDF | View/Open |
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