Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/16634
Title: Implementation of decoders for LDPC block codes and LDPC convolutional codes based on GPUs
Authors: Zhao, Y
Lau, FCM 
Keywords: CUDA
Graphics processing unit (GPU)
LDPC
LDPC convolutional code
LDPC decoder
LDPCCC decoder
OpenMP
Parallel computing
Issue Date: 2014
Publisher: Institute of Electrical and Electronics Engineers
Source: IEEE transactions on parallel and distributed systems, 2014, v. 25, no. 3, 6470607, p. 663-672 How to cite?
Journal: IEEE transactions on parallel and distributed systems 
Abstract: In this paper, efficient LDPC block-code decoders/simulators which run on graphics processing units (GPUs) are proposed. We also implement the decoder for the LDPC convolutional code (LDPCCC). The LDPCCC is derived from a predesigned quasi-cyclic LDPC block code with good error performance. Compared to the decoder based on the randomly constructed LDPCCC code, the complexity of the proposed LDPCCC decoder is reduced due to the periodicity of the derived LDPCCC and the properties of the quasi-cyclic structure. In our proposed decoder architecture, (Γ) (Γ) is a multiple of a warp) codewords are decoded together, and hence, the messages of (Γ) codewords are also processed together. Since all the (Γ) codewords share the same Tanner graph, messages of the (Γ) distinct codewords corresponding to the same edge can be grouped into one package and stored linearly. By optimizing the data structures of the messages used in the decoding process, both the read and write processes can be performed in a highly parallel manner by the GPUs. In addition, a thread hierarchy minimizing the divergence of the threads is deployed, and it can maximize the efficiency of the parallel execution. With the use of a large number of cores in the GPU to perform the simple computations simultaneously, our GPU-based LDPC decoder can obtain hundreds of times speedup compared with a serial CPU-based simulator and over 40 times speedup compared with an eight-thread CPU-based simulator.
URI: http://hdl.handle.net/10397/16634
ISSN: 1045-9219
EISSN: 1558-2183
DOI: 10.1109/TPDS.2013.52
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