A general strategy to achieve colossal permittivity and low dielectric loss through constructing insulator/semiconductor/insulator multilayer structures

Abstract

In this work, we propose a route to realize high-performance colossal permittivity (CP) by creating multilayer structures of insulator/semiconductor/insulator. To prove the new concept, we made heavily reduced rutile TiO2 via annealing route in Ar/H2 atmosphere. Dielectric studies show that the maximum dielectric permittivity (~ 3.0 × 104) of our prepared samples is about 100 times higher than that (~ 300) of conventional TiO2. The minimum dielectric loss is 0.03 (at 104–105 Hz). Furthermore, CP is almost independent of the frequency (100–106 Hz) and the temperature (20–350 K). We suggest that the colossal permittivity is attributed to the high carrier concentration of the inner TiO2 semiconductor, while the low dielectric loss is due to the presentation of the insulator layer on the surface of TiO2. The method proposed here can be expanded to other material systems, such as semiconductor Si sandwiched by top and bottom insulator layers of Ga2O3.