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http://hdl.handle.net/10397/750
Title: | Techniques for improving block error rate of LDPC decoders | Authors: | Zheng, X Lau, FCM Tse, CKM Wong, SC |
Issue Date: | 2006 | Source: | ISCAS 2006 : 2006 IEEE International Symposium on Circuits and Systems : circuits and systems: at crossroads of life and technology : proceedings : May 21-24, 2006, Island of Kos, Greece, p. 2261-2264 | Abstract: | In the study of Low-Density-Parity-Check (LDPC) codes, most researchers are interested in their bit error rate performance. However, BLock Error Rate (BLER) is another important measure of the system performance because it provides the rate at which the blocks/packets need to be re-sent again - the smaller the better. In this paper, we apply a simple feedback technique to the decoding of LDPC codes. Extensive simulations have been performed. Results show that the proposed method can effectively improve the BLER of the codes at the waterfall region while not degrading the BER performance at the high SNR region. | Keywords: | Computer simulation Decoding Errors Signal to noise ratio |
Publisher: | IEEE | ISBN: | 0-7803-9390-2 | Rights: | © 2006 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holders. |
Appears in Collections: | Conference Paper |
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ldpc-decoders_06.pdf | 1.16 MB | Adobe PDF | View/Open |
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