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dc.contributorDepartment of Applied Physics-
dc.creatorHuang, Y-
dc.creatorXu, JP-
dc.creatorLiu, L-
dc.creatorCheng, ZX-
dc.creatorLai, PT-
dc.creatorTang, WM-
dc.date.accessioned2018-03-29T09:33:55Z-
dc.date.available2018-03-29T09:33:55Z-
dc.identifier.issn1757-8981-
dc.identifier.urihttp://hdl.handle.net/10397/74805-
dc.description2017 2nd International Conference on Advanced Materials Research and Manufacturing Technologies, AMRMT 2017, Phuket, Thailand, 2-5 August, 2017en_US
dc.language.isoenen_US
dc.publisherInstitute of Physics Publishingen_US
dc.rightsContent from this work may be used under the terms of the Creative Commons Attribution 3.0 licence (https://creativecommons.org/licenses/by/3.0/). Any further distribution of this work must maintain attribution to the author(s) and the title of the work, journal citation and DOI.en_US
dc.rightsPublished under licence by IOP Publishing Ltden_US
dc.rightsThe following publication Huang, Y., Xu, J. P., Liu, L., Cheng, Z. X., Lai, P. T., & Tang, W. M. (2017, September). Interfacial and electrical properties of Ge MOS capacitor by ZrLaON passivation layer and fluorine incorporation. In IOP Conference Series. Materials Science and Engineering, 229(1), 012018 is available at https://doi.org/10.1088/1757-899X/229/1/012018en_US
dc.titleInterfacial and electrical properties of Ge MOS capacitor by ZrLaON passivation layer and fluorine incorporationen_US
dc.typeConference Paperen_US
dc.identifier.volume229-
dc.identifier.issue1-
dc.identifier.doi10.1088/1757-899X/229/1/012018-
dcterms.abstractGe Metal-Oxide-Semiconductor (MOS) capacitor with HfTiON/ZrLaON stacked gate dielectric and fluorine-plasma treatment is fabricated, and its interfacial and electrical properties are compared with its counterparts without the ZrLaON passivation layer or the fluorine-plasma treatment. Experimental results show that the sample exhibits excellent performances: low interface-state density (3.7×1011 cm-2eV-1), small flatband voltage (0.21 V), good capacitance-voltage behavior, small frequency dispersion and low gate leakage current (4.41×10-5 A/cm2 at Vg = Vfb + 1V). These should be attributed to the suppressed growth of unstable Ge oxides on the Ge surface during gate-dielectric annealing by the ZrLaON interlayer and fluorine incorporation, thus greatly reducing the defective states at/near the ZrLaON/Ge interface and improving the electrical properties of the device.-
dcterms.accessRightsopen accessen_US
dcterms.bibliographicCitationIOP Conference Series: Materials Science and Engineering, 2017, v. 229, no. 1, 012018-
dcterms.issued2017-
dc.identifier.scopus2-s2.0-85033783911-
dc.relation.conferenceInternational Conference on Advanced Materials Research and Manufacturing Technologies [AMRMT]-
dc.identifier.artn012018-
dc.identifier.rosgroupid2017005266-
dc.description.ros2017-2018 > Academic research: refereed > Publication in refereed journal-
dc.description.validate201803 bcma-
dc.description.oaVersion of Recorden_US
dc.identifier.FolderNumberOA_IR/PIRAen_US
dc.description.pubStatusPublisheden_US
dc.description.oaCategoryCCen_US
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