Please use this identifier to cite or link to this item:
http://hdl.handle.net/10397/214
DC Field | Value | Language |
---|---|---|
dc.contributor | Department of Computing | - |
dc.creator | Zhang, DD | - |
dc.creator | Pal, SK | - |
dc.date.accessioned | 2014-12-11T08:27:11Z | - |
dc.date.available | 2014-12-11T08:27:11Z | - |
dc.identifier.issn | 1045-9227 | - |
dc.identifier.uri | http://hdl.handle.net/10397/214 | - |
dc.language.iso | en | en_US |
dc.publisher | Institute of Electrical and Electronics Engineers | en_US |
dc.rights | © 2000 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. | en_US |
dc.rights | This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. | en_US |
dc.subject | Neuro-fuzzy clustering | en_US |
dc.subject | Systolic array | en_US |
dc.subject | Very large scale integration (VLSI) | en_US |
dc.title | A fuzzy clustering neural networks (FCNs) system design methodology | en_US |
dc.type | Journal/Magazine Article | en_US |
dc.identifier.spage | 1174 | - |
dc.identifier.epage | 1177 | - |
dc.identifier.volume | 11 | - |
dc.identifier.issue | 5 | - |
dc.identifier.doi | 10.1109/72.870048 | - |
dcterms.abstract | A system design methodology for fuzzy clustering neural networks (FCNs) is presented. This methodology emphasizes coordination between FCN model definition, architectural description, and systolic implementation. Two mapping strategies both from FCN model to system architecture and from the given architecture to systolic arrays are described. The effectiveness of the methodology is illustrated by: 1) applying the design to an effective FCN model; 2) developing the corresponding parallel architecture with special feedforward and feedback paths; and 3) building the systolic array (SA) suitable for very large scale integration (VLSI) implementation. | - |
dcterms.accessRights | open access | en_US |
dcterms.bibliographicCitation | IEEE transactions on neural networks, Sept. 2000, v. 11, no. 5, p.1174-1177 | - |
dcterms.isPartOf | IEEE transactions on neural networks | - |
dcterms.issued | 2000-09 | - |
dc.identifier.isi | WOS:000089508300012 | - |
dc.identifier.scopus | 2-s2.0-0034270238 | - |
dc.identifier.rosgroupid | r03505 | - |
dc.description.ros | 2000-2001 > Academic research: refereed > Publication in refereed journal | - |
dc.description.oa | Version of Record | en_US |
dc.identifier.FolderNumber | OA_IR/PIRA | en_US |
dc.description.pubStatus | Published | en_US |
dc.description.oaCategory | VoR allowed | en_US |
Appears in Collections: | Journal/Magazine Article |
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