Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/1539
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dc.contributorDepartment of Electrical Engineering-
dc.creatorChan, YH-
dc.creatorSiu, WC-
dc.date.accessioned2014-12-11T08:28:31Z-
dc.date.available2014-12-11T08:28:31Z-
dc.identifier.issn1057-7122-
dc.identifier.urihttp://hdl.handle.net/10397/1539-
dc.language.isoenen_US
dc.publisherInstitute of Electrical and Electronics Engineersen_US
dc.rights© 1992 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.en_US
dc.rightsThis material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.en_US
dc.subjectCMOS integrated circuitsen_US
dc.subjectVLSIen_US
dc.subjectDigital arithmeticen_US
dc.subjectDigital signal processing chipsen_US
dc.subjectDiscrete cosine transformsen_US
dc.subjectSpecial purpose computersen_US
dc.titleOn the realization of discrete cosine transform using the distributed arithmeticen_US
dc.typeJournal/Magazine Articleen_US
dc.identifier.spage705-
dc.identifier.epage712-
dc.identifier.volume39-
dc.identifier.issue9-
dc.identifier.doi10.1109/81.250161-
dcterms.abstractIn this paper, we propose a unified approach for the realization of forward and inverse discrete cosine transforms. By making use of this approach, one can realize an odd prime length DCT/IDCT with two half-length convolutions without extra overheads in terms of the number of multiplications. This formulation is most suitable for the realization using the distributed arithmetic. In such a case, typical convolvers can be used as the core unit for the hardware implementation of the transforms. Hence, an efficient unified DCT/IDCT chip can be designed. A 2-D 11 x 11 unified DCT/IDCT chip is also proposed to demonstrate the superiority of the proposed formulation in this paper. The proposed architecture can easily meet the speed requirement of 14.3-MHz real-time operation with the current 2-μm CMOS technology.-
dcterms.accessRightsopen accessen_US
dcterms.bibliographicCitationIEEE transactions on circuits and systems. I, Fundamental theory and applications, Sept. 1992, v. 39, no. 9, p. 705-712-
dcterms.isPartOfIEEE transactions on circuits and systems. I, Fundamental theory and applications-
dcterms.issued1992-09-
dc.identifier.isiWOS:A1992KK11700001-
dc.description.oaVersion of Recorden_US
dc.identifier.FolderNumberOA_IR/PIRAen_US
dc.description.pubStatusPublisheden_US
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