Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/113667
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Title: Delayed memory unit : modeling temporal dependency through delay gate
Authors: Sun, P
Wu, J 
Zhang, M
Devos, P
Botteldooren, D
Issue Date: Jun-2025
Source: IEEE transactions on neural networks and learning systems, June 2025, v. 36, no. 6, p. 10808-10818
Abstract: Recurrent neural networks (RNNs) are widely recognized for their proficiency in modeling temporal dependencies, making them highly prevalent in sequential data processing applications. Nevertheless, vanilla RNNs are confronted with the well-known issue of gradient vanishing and exploding, posing a significant challenge for learning and establishing long-range dependencies. Additionally, gated RNNs tend to be over-parameterized, resulting in poor computational efficiency and network generalization. To address these challenges, this article proposes a novel delayed memory unit (DMU). The DMU incorporates a delay line structure along with delay gates into vanilla RNN, thereby enhancing temporal interaction and facilitating temporal credit assignment. Specifically, the DMU is designed to directly distribute the input information to the optimal time instant in the future, rather than aggregating and redistributing it over time through intricate network dynamics. Our proposed DMU demonstrates superior temporal modeling capabilities across a broad range of sequential modeling tasks, utilizing considerably fewer parameters than other state-of-the-art gated RNN models in applications such as speech recognition, radar gesture recognition, ECG waveform segmentation, and permuted sequential (PS) image classification.
Keywords: Delay gate
Delay line
Recurrent neural network (RNN)
Speech recognition
Time series analysis
Publisher: Institute of Electrical and Electronics Engineers
Journal: IEEE transactions on neural networks and learning systems 
ISSN: 2162-237X
EISSN: 2162-2388
DOI: 10.1109/TNNLS.2024.3490833
Rights: © 2024 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
The following publication P. Sun, J. Wu, M. Zhang, P. Devos and D. Botteldooren, "Delayed Memory Unit: Modeling Temporal Dependency Through Delay Gate," in IEEE Transactions on Neural Networks and Learning Systems, vol. 36, no. 6, pp. 10808-10818, June 2025 is available at https://doi.org/10.1109/TNNLS.2024.3490833.
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