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http://hdl.handle.net/10397/88793
Title: | Hardware design of concatenated zigzag hadamard encoder/decoder system with high throughput | Authors: | Jiang, S Lau, FCM Sham, CW |
Issue Date: | 2020 | Source: | IEEE access, . . 2020, , v. 8, p. 165298-165306 | Abstract: | Both turbo Hadamard codes and concatenated zigzag Hadamard codes are ultimate-Shannon-limit-approaching channel codes. The former one requires the use of Bahl-Cocke-Jelinek-Raviv (BCJR) in the iterative decoding process, making the decoder structure more complex and limiting its throughput. The latter one, however, does not involve BCJR decoding. Hence its decoder structure can be much simpler and can potentially operate at a much higher throughput. In this paper, we investigate the hardware design of a concatenated zigzag Hadamard encoder/decoder system and implement it onto an FPGA board. We design a decoder capable of decoding multiple codewords at the same time, and the proposed system can operate with a throughput of 1.44 Gbps - increase of 50% compared with the turbo Hadamard encoder/decoder system. As for the error performance, the encoder/decoder system with a 6-bit quantization achieves a bit error rate of 2 x 10(-5) at E-b/N-0 = -0.2 dB. | Keywords: | Concatenated zigzag hadamard code Hardware design High throughput Turbo hadamard code Zigzag hadamard code |
Publisher: | Institute of Electrical and Electronics Engineers | Journal: | IEEE access | EISSN: | 2169-3536 | DOI: | 10.1109/ACCESS.2020.3022537 | Rights: | This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ The following publication Jiang, S., Lau, F. C. M., & Sham, C. W. (2020). Hardware design of concatenated zigzag hadamard encoder/decoder system with high throughput. IEEE Access, 8, 165298-165306 is available at https://dx.doi.org/10.1109/ACCESS.2020.3022537 |
Appears in Collections: | Journal/Magazine Article |
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