Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/68714
Title: Decoding device
Other Titles: 译码装置
Authors: Cen, CR 
Chen, X 
Tan, WW 
Zhao, Y 
Liu, CM 
Yu, F
Issue Date: 16-Jul-2014
Publisher: 中华人民共和国国家知识产权局
Source: 中国专利 ZL 201180001583.4 How to cite?
Abstract: The invention relates a decoding device. The decoding device comprises a storage module that is used for storing channel information of various variable nodes in bipartite graph of low-density parity-check QC-LDPC codes and external information transmitted between various check nodes and various variable nodes of the QC-LDPC codes in the process of iterative decoding for the QC-LDPC, wherein the external information transmitted between any two conjoint check node C and variable node V of the QC-LDPC codes store on the same storage position of the storage module; an updating module that is used for computing the external information transmitted between various check nodes and various variable nodes of the QC-LDPC codes and writing the computed external information in the storing module to update the external information stored in the storage module by the way of dividing various check nodes of the QC-LDPC codes into multi-layer check nodes and layer-to-layer processing according to the channel information and the external information stored on the storage module in the process of each iterative decoding of the QC-LDPC codes, and is used for computing posterior probability information of various variable nodes of the QC-LDPC codes according to the channel information and the external information stored on the storage module and the computed external information; and a computing module that is used for computing decision value of various code bit of the QC-LDPC codes according to the computed posterior probability information of various variable nodes of the QC-LDPC codes. The decoding device can decrease the required storing resource and can reduce hardware implement complexity of the decoding device.
本发明涉及一种译码装置,包括:存储模块,用于存储准循环低密度奇偶校验QC-LDPC码的二分图的各个变量节点的信道信息和在对所述QC-LDPC码进行迭代译码过程中在所述QC-LDPC码的各个校验节点和各个变量节点之间传递的外部信息,其中,在所述QC-LDPC码的任意两个相连的校验节点C和变量节点V之间传递的外部信息存储在所述存储模块的相同存储位置中;更新模块,用于在所述QC-LDPC码的每一次迭代译码过程中,根据所述存储模块所存储的信道信息和外部信息,按照将所述QC-LDPC码的各个校验节点划分为多层校验节点并逐层处理的方式,计算在所述QC-LDPC码的各个校验节点和各个变量节点之间传递的外部信息并且将所计算的外部信息写入所述存储模块以更新所述存储模块所存储的外部信息,以及用于根据所述存储模块所存储的信道信息和外部信息以及所计算的外部信息来计算所述QC-LDPC码的各个变量节点的后验概率信息;以及,计算模块,用于根据所计算的所述QC-LDPC码的各个变量节点的后验概率信息,计算所述QC-LDPC码的各个码位的判决取值。利用该译码装置,减少了所需的存储资源,降低了译码装置的硬件实现复杂度。
URI: http://hdl.handle.net/10397/68714
Rights: 专利权人: The Hong Kong Polytechnic University.
Appears in Collections:Patent

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