Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/66904
Title: A 3.0 gb/s throughput hardware-efficient decoder for cyclically-coupled QC-LDPC codes
Authors: Lu, Q
Fan, JF
Sham, CW
Tam, WM
Lau, FCM 
Keywords: Cyclically-coupled QC-LDPC code
Decoder architecture
FPGA implementation
QC-LDPC code
Issue Date: 2016
Publisher: Institute of Electrical and Electronics Engineers
Source: IEEE transactions on circuits and systems. I, Regular papers, Jan. 2016, v. 63, no. 1, p. 134-145 How to cite?
Journal: IEEE transactions on circuits and systems. I, Regular papers 
URI: http://hdl.handle.net/10397/66904
ISSN: 1549-8328
EISSN: 1558-0806
DOI: 10.1109/TCSI.2015.2510619
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