Routability-driven floorplanning of analog and mixed-signal circuits

Abstract

The exponential increase in scale and complexity of very large scale integrated circuits (VLSI) poses a great challenge to the present electronic design automation (EDA) techniques. As an essential step in the whole EDA layout synthesis, placement design is attracting more and more attention, especially the one for analog and mixed-signal integrated circuits. Recently, the experts in this field observe a variety of analog-specific layout constraints to obtain high-performance placements. These constraints include symmetry, alignment, boundary, preplace, abutment, range and maximum separation and addition-ally the routability of the placement. In order to solve this multi-objective placement problem, two different approaches are proposed in this thesis. One employs the sequence pair (SP) representation to solve the placement problem with mixed constraints. The routability of the placement is improved by performing module expansion according to the net congestion probability in the circuits. The other one applies the polish expression (PE) representation and utilizes the characteristics of the slicing structures to achieve better placement results. Experimental results on area and routability demonstrate that the two approaches are effective and feasible in solving the complex placement problem.