Please use this identifier to cite or link to this item:
http://hdl.handle.net/10397/76866
| Title: | Decoder architecture for cyclically-coupled quasi-cyclic low-density parity-check codes | Authors: | Sham, CW Fan, J Tam, WM Lu, Q Lau, CM |
Issue Date: | 21-Nov-2017 | Source: | US Patent 9,825,650 B2. Washington, DC: US Patent and Trademark Office, 2017. | Abstract: | This invention provides a cyclically-coupled (CC-) quasi-cyclic (QC-) low-density parity-check (LDPC) code and its decoder architecture. The essence of the invention is to introduce the convolutional nature to a plurality of individual block codes internally so as to form a resultant block code with a prolonged code length while slightly increasing the hardware complexity in decoder realization. The CC-QC-LDPC code is formed by cyclically coupling a plurality of sub-codes each being a QC-LDPC code such that overlapping of some variable nodes between two consecutive sub-codes results. The decoder comprises plural sub-decoders each configured to decode the channel messages for one sub-code. The sub-decoders are arranged in a ring shape such that an individual sub-decoder is configured to communicate edge messages with two neighboring sub-decoders adjacent to said individual sub-decoder in the decoding of the channel messages. The sub-decoders are configured to operate concurrently for simultaneously decoding individual sub-codes. | Rights: | Assignee: The Hong Kong Polytechnic University |
| Appears in Collections: | Patent |
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| File | Description | Size | Format | |
|---|---|---|---|---|
| us9825650b2.pdf | 1.23 MB | Adobe PDF | View/Open |
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