Study of resistive switching in GeSx/Ag system for neuromorphic computing applications

Abstract

As a promising building block of the emerging neuromorphic computing hardware, memory devices with multi-functionalities realized in a single memory device are highly demanded. However, demonstration of such memory devices with multi-functionalities remains limited. In this thesis work, Ag/GeSx-based memory devices with coexisted non-volatile and volatile resistive switching behaviors were extensively investigated, enabling realization of multiple neuromorphic computing applications in a single memory device. The following results have been achieved. Firstly, non-volatile resistive switching behavior of the memory devices was investigated. Due to the small thickness of the dielectric layer, ultralow switching voltage was achieved leading to ultralow power consumption of the memory devices. With such outstanding performances in terms of the ultralow switching voltage (within 0.15 V) and switching energy (within 1 pJ), achieved with the memory devices, their data retention and endurance properties were also found to meet the high industry requirements for traditional memory application. For determination of switching speed and for estimation of switching energy of the memory devices, a technique of switching time measurement was proposed and successfully implemented. Other important resistive switching characteristics of the memory devices such as frequency dependence and electrode size dependence were also investigated. While frequency dependence demonstrates potential applications of the memory devices as multistate memory and in hardware realization of artificial neural network (ANN), electrode size dependence confirms the filamentary-based nature of the resistive switching in the non-volatile memory mode. Spike timing dependent plasticity (STDP) was also investigated demonstrating potential application of the memory devices in hardware realization of spiking neural network (SNN). Realization of a complementary resistive switch was also demonstrated. Furthermore, volatile resistive switching behavior of the memory devices was investigated. Besides non-volatile resistive switching behavior which is of the filamentary-based nature and occurs in lower resistance range, the memory devices present unprecedented volatile resistive switching behavior which occurs in higher resistance range. Such volatile resistive switching behavior allows realization of learning/relearning and forgetting behaviors that can be associated with synaptic plasticity and ultimately leads to reservoir computing hardware realization. Underlying physics of such volatile resistive switching behavior was extensively investigated by means of in situ transmission electron microscopy characterization, and the nature of the resistive switching of the memory device in the volatile memory mode was found to be diffusion-based. Finally, non-volatile and volatile resistive switching behaviors of the memory devices were combined together for hardware realization of image classification. The setup proposed for hardware realization of image classification was demonstrated. Essentially, it consists of a crossbar array of memory devices working in the non-volatile memory mode which is implemented as a data library unit and an identical memory device working in the volatile memory mode which is implemented as a dynamic reservoir. Such dynamic reservoir shrinks the volume of the visual data to be processed by the setup or, in other words, pre-processes the visual data. It was demonstrated that a setup with implementation of such dynamic reservoir outperforms an analogous setup that does not have such dynamic reservoir and processes the visual data directly, without reservoir computing data pre-processing. Image classification with English alphabetic letters A-Z and digits 0-9 was successfully demonstrated in a simulation with performances of physical memory devices. Overall, the results presented in this thesis work pave the way towards complete hardware realization of the proposed setup for image classification with English alphabetic letters A-Z and digits 0-9. Moreover, the application of the setup, which is essentially a combination of traditional memory application and reservoir computing hardware realization, can be extended to image classification with the visual data of a higher complexity. Besides, it was demonstrated that the memory devices can be potentially utilized as multistate memory and a complementary resistive switch as well as in hardware realization of such neuromorphic computing applications as ANN and SNN.