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Title: New storage scheme for conflict-free vector access
Authors: Lam, KM 
Siu, WC 
Yin, JX
Tse, KM
Issue Date: 1993
Publisher: IEEE
Source: Proceedings of the 10th IEEE Region Conference on Computer, Communication, Control and Power Engineering, 1993, p. 32-35 How to cite?
Abstract: Investigations into data storage schemes for parallel memory system of vector processing have been mainly focused on low-order interleaved scheme, skewed scheme and XOR scheme. In this paper, a new interleaved storage scheme, namely k-row interleaved scheme, is suggested and investigated. This scheme allocates k consecutive data of a vector onto one memory module sequentially and then the next k consecutive data onto the next memory module. The address mapping functions are devised and the performance of this scheme is evaluated. It is found that this scheme improves the average performance for vector access over the previous schemes. The address generation hardware is also shown to be simple.
Description: Proceedings of the 1993 IEEE Region 10 Conference on Computer, Communication, Control and Power Engineering (TENCON '93). Part 1 (of 5), Beijing, China, 19-21 October 1993
ISBN: 0-7803-1233-3
Appears in Collections:Conference Paper

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