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Title: On-demand block-level address mapping in large-scale NAND flash storage systems
Authors: Chen, R
Qin, Z
Wang, Y
Liu, D
Shao, Z 
Guan, Y
Keywords: Block-level mapping
NAND flash memory
On demand
Storage management
Two-level cache
Issue Date: 2015
Publisher: Institute of Electrical and Electronics Engineers
Source: IEEE transactions on computers, 2015, v. 64, no. 6, p. 1729-1741 How to cite?
Journal: IEEE transactions on computers 
Abstract: The density of flash memory chips has doubled every two years in the past decade and the trend is expected to continue. The increasing capacity of NAND flash memory leads to large RAM footprint on address mapping management. This paper proposes a novel Demand-based block-level Address mapping scheme with a two-level Caching mechanism (DAC) for large-scale NAND flash storage systems. The objective is to reduce RAM footprint without excessively compromising system response time. In our technique, the block-level address mapping table is stored in fixed pages (called the translation pages) in the flash memory. Considering temporal locality that workloads exhibit, we maintain one cache in RAM to store the on-demand address mapping entries. Meanwhile, by exploring both spatial locality and access frequency of workloads with another two caches, the second-level cache is designed to cache selected translation pages. In such a way, both the most-frequently-accessed and sequentially accessed address mapping entries can be stored in the cache so the cache hit ratio can be increased and the system response time can be improved. To the best of our knowledge, this is the first work to reduce the RAM cost by employing the demand-based approach on block-level address mapping schemes. The experiments have been conducted on a real embedded platform. The experimental results show that our technique can effectively reduce the RAM footprint while maintaining similar average system response time compared with previous work.
ISSN: 0018-9340
EISSN: 1557-9956
DOI: 10.1109/TC.2014.2329680
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