Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/8010
Title: Architecture of wavelet-based frame skipping transcoder
Authors: Fung, KT
Siu, WC 
Issue Date: 2003
Source: Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03, 2003, v. 2, 1281092, p. 1229-1232 How to cite?
Abstract: A new architecture of wavelet based frame skipping transcoding process for multipoint video conferencing is proposed in this paper. The work involves new structures for a video coder and a transcoder which are wavelet-based. The video transcoder extracts information of motion activities from the video bitstream produced by a wavelet-based video coder. Using the proposed frame skipping process in the wavelet domain, temporal scalability can be achieved. The video quality of inactive sub-sequences can be easily adjusted using the video combiner. This is achieved by discarding fine details of the bitstream or performing frame skipping in the wavelet domain. In other words, more bits can be reallocated to active sub-sequences to achieve a good visual quality with smooth motion. In addition, the video coder is region-based so that different wavelet kernels can be used for the foreground and background. This setting can, on one hand, reduce the computational complexity significantly. On the other hand, by considering unequal importance of various regions, a high video quality for foreground objects is always guaranteed whilst an acceptable background quality can also be maintained even under low bitrate environments. Since the video transcoder only needs to rearrange the video quality level according to their motion activities or performing frame skipping in wavelet domain, a significant saving in computational complexity can be achieved as compared to the conventional video combiner using transcoding approach. The new video coder and transcoder are then used to realize a multipoint video conferencing system. Experimental results are included at the end of the paper, which show a good improvement in performance due to the proposed architecture.
Description: 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03, Nanjing, 14-17 December 2003
URI: http://hdl.handle.net/10397/8010
ISBN: 0780377028
9780780377028
DOI: 10.1109/ICNNSP.2003.1281092
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