Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/79874
Title: Accelerating cycle-accurate system-level simulations through behavioral templates
Authors: Mahapatra, A 
Liu, YD 
Schafer, BC
Keywords: Heterogeneous SoCs
Hardware accelerators
High-level synthesis
Templates
Acceleration
Simulation
Issue Date: 2018
Publisher: Elsevier
Source: Integration, the VLSI journal, June 2018, v. 62, p. 282-291 How to cite?
Journal: Integration, the VLSI journal 
Abstract: This work presents a method to accelerate the running time of cycle-accurate system-level simulations. The proposed method substitutes the computational units specified at the RT-level or behavioral level in the system with fast templates of the exact latency of its original design and thus, preserving the performance measurement accuracy. The method has been extended to deal with control dependencies inside loops in order to maintain high modelling accuracies under any condition. Experimental results show that our proposed method works well speeding up individual accelerator kernels by up to 8 and 15x. Moreover when used to explore entire SoC configurations it achieves similar result as using the exact models while achieving an average speedup of 4.7x.
URI: http://hdl.handle.net/10397/79874
ISSN: 0167-9260
DOI: 10.1016/j.vlsi.2018.03.014
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