Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/77680
Title: Configurable SoC in-situ hardware/software co-design design space exploration
Authors: Xu, S
Schafer, BC
Liu, Y 
Keywords: Behavioral IP
Configurable SoC
Design space exploration
Hardware accelerators
Hardware/Software co-design
High-level synthesis
Issue Date: 2017
Publisher: Institute of Electrical and Electronics Engineers
Source: Proceedings - 35th IEEE International Conference on Computer Design, ICCD 2017, 8119261, p. 509-512 How to cite?
Abstract: This work presents a method to characterize heterogeneous hardware/software systems mapped onto Configurable SoCs (CSoC) in situ, where in situ implies that the CSoC being characterized is also the final target platform. The result of our proposed method is a trade-off curve of different configurations with unique area vs. performance characteristics, each of which uses a different micro-architecture for the accelerators. Our work has been prototyped on a DE1-SoC FPGA board containing a Cyclone V SoC FPGA with two ARM cores and reconfigurable fabric onto which the complete trade-off curves with dominating designs for each BIP are mapped. A fast heuristic method is proposed, which compared to an exhaustive search method, leading to the optimal solution, is slightly worse while on average 15.2 faster, showing that it can lead to very good results quickly. The proposed method is also compared to a simulation-based offline method. In situ characterization is able to speed up the exploration by on average 25.6, while being more accurate.
URI: http://hdl.handle.net/10397/77680
ISBN: 9.78154E+12
DOI: 10.1109/ICCD.2017.88
Appears in Collections:Conference Paper

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