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Title: Hardware Trojan avoidance and detection for dynamically re-configurable FPGAs
Authors: Veeranna, N 
Schafer, BC
Keywords: Hardware Trojan
Issue Date: 2016
Publisher: Institute of Electrical and Electronics Engineers
Source: 15th International Conference on Field-Programmable Technology (FPT), Xian, People's Republic of China, Dec 7-9, 2016, p. 193-196 How to cite?
Abstract: Multi-Context Runtime Reconfigurable FPGAs have unique characteristics that make them extremely vulnerable to Hardware Trojan (HT). These FPGA families reconfigure themselves every clock cycle updating the functionality of the data path. A State Transition Controller (STC) typically holds the configuration code for each of the contexts. This architecture makes these type of architectures very efficient, but also extremely vulnerable to malicious alterations across any of the steps from design to fabrication of the FPGA. This work specifically targets the detection, but also the avoidance of HT being triggered in runtime reconfigurable FPGAs and in particular Coarse-Grained Runtime Reconfigurable Arrays (CGRRA). Experimental results show that our proposed method is very effective and has very little power overhead with no net area overhead. Index Terms-Hardware Trojan, CGRRA
ISBN: 978-1-5090-5602-6
Appears in Collections:Conference Paper

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