Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/74915
Title: Learning-based interconnect-aware dataflow accelerator optimization
Authors: Liu, S 
Schafer, BC
Issue Date: 2017
Publisher: Institute of Electrical and Electronics Engineers Inc.
Source: 2017 27th International Conference on Field Programmable Logic and Applications, FPL 2017, 2017, 8056821 How to cite?
Abstract: The interconnect is the Achilles heel of FPGAs. It currently dominates the delay and leads to high power consumption. It is thus, imperative to take it into account when designing complex FPGA systems. In this work, we propose a learning-based method for data-flow systems build out of multiple individual components directly connected and find a set of optimal configurations with unique area vs. throughput trade-offs by time-multiplexing their interconnects. These type of configurations are prevalent in FPGA designs where one block streams data to the next one, i.e., jpeg encoders. One uniqueness of this work is that it uses advanced features of state-of-the-art HLS tools that enable automatic pin multiplexing. This feature implies that logic IO ports are time multiplexed automatically, which affects not only the performance of the design, but also the area, and the interconnect complexity, leading to system configurations with unique area vs. performance trade-offs. Pin multiplexing is not feasible at the RT-level where each design has to be manually optimized. Experimental results show that the method is accurate and fast when compared to an exhaustive search as well as other state-of-the-art methods.
Description: 27th International Conference on Field Programmable Logic and Applications, FPL 2017, Ghent, Belgium, 4-6 September, 2017
URI: http://hdl.handle.net/10397/74915
ISBN: 9789090304281
DOI: 10.23919/FPL.2017.8056821
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