Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/74904
Title: A novel ReRAM-based processing-in-memory architecture for graph computing
Authors: Han, L 
Shen, Z 
Shao, Z 
Huang, HH
Li, T
Issue Date: 2017
Publisher: Institute of Electrical and Electronics Engineers Inc.
Source: NVMSA 2017 - 6th IEEE Non-Volatile Memory Systems and Applications Symposium, 2017, 8064464 How to cite?
Abstract: Graph algorithms such as breadth-first search (BFS) have been gaining ever-increasing importance in the era of Big Data. However, the memory bandwidth remains the key performance bottleneck for graph processing. To address this problem, we utilize processing-in-memory (PIM), combined with non-volatile metal-oxide resistive random access memory (ReRAM), to improve the performance of both computation and I/O. The idea is to integrate the computation logic into the memory in which the data accesses are located. We propose and implement a new ReRAM-based processing-in-memory architecture called RPBFS, in which graphs can be processed and persistently stored. We also design an efficient graph traversal scheme. Benefited from low data movement overhead and bank-level parallel computation, RPBFS shows a significant performance improvement compared with both the CPU-based and GPU-based BFS implementations. On a suite of real world graphs, our architecture yields up to 33.8× speedup.
Description: 6th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2017, Hsinchu, Taiwan, 16-18 August, 2017
URI: http://hdl.handle.net/10397/74904
ISBN: 9781538617687
DOI: 10.1109/NVMSA.2017.8064464
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