Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/68786
Title: An analytical approach to floorplanning for hierarchical building blocks layout
Authors: Ying, CS
Wong, JSL 
Issue Date: 1989
Publisher: Institute of Electrical and Electronics Engineers
Source: IEEE transactions on computer-aided design of integrated circuits and systems, 1989, v. 8, no. 4, p. 403-412 How to cite?
Journal: IEEE transactions on computer-aided design of integrated circuits and systems 
Abstract: This paper describes an analytical approach for the floorplanning of rectangular blocks with various constraints on their connection and dimension such that the total wire length and area of the resulting floorplan are minimized. The approach consists of two phases: relative placement and spacing. Relative placement places the building blocks in a plane such that the topology of the blocks satisfies the combined goal of short interconnection and small bounding area for a given aspect ratio. The spacing phase removes the overlap in the floorplan resulting from relative placement by moving and reshaping the blocks. Both phases are modeled heuristically as unconstrained minimization problem. The constraint on the shape of floorplan is met using a bounding penalty function. Indirect connections between large blocks are taken into account for more efficient area utilization. The floorplanning algorithm has been implemented. Experimental results show that the approach is effective for handling floorplanning under various kinds of constraints.
URI: http://hdl.handle.net/10397/68786
ISSN: 0278-0070
EISSN: 1937-4151
DOI: 10.1109/43.29594
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