Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/67072
Title: Efficient and reliable high-level synthesis design space explorer for FPGAs
Authors: Liu, D
Schafer, BC
Issue Date: 2016
Publisher: Institute of Electrical and Electronics Engineers
Source: 2016 26th International Conference on Field-Programmable Logic and Applications (FPL), Aug 29-Aug 2, 2016, Ecole Polytechnique Federale de Lausanne, Lausanne, Switzerland How to cite?
URI: http://hdl.handle.net/10397/67072
Appears in Collections:Conference Paper

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