Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/66372
Title: Enabling high-level synthesis resource sharing design space exploration in FPGAs through automatic internal bitwidth adjustments
Authors: Schafer, BC
Keywords: Design space exploration (DSE)
Field-programmable gate arrays (FPGAs)
High-level synthesis (HLS)
Resource sharing
Issue Date: 2017
Publisher: Institute of Electrical and Electronics Engineers
Source: IEEE transactions on computer-aided design of integrated circuits and systems, Jan. 2017, v. 36, no. 1, p. 97-105 How to cite?
Journal: IEEE transactions on computer-aided design of integrated circuits and systems 
URI: http://hdl.handle.net/10397/66372
ISSN: 0278-0070
EISSN: 1937-4151
DOI: 10.1109/TCAD.2016.2550501
Appears in Collections:Journal/Magazine Article

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