Please use this identifier to cite or link to this item:
http://hdl.handle.net/10397/66265
DC Field | Value | Language |
---|---|---|
dc.contributor | Department of Electronic and Information Engineering | en_US |
dc.contributor | Chinese Mainland Affairs Office | en_US |
dc.creator | Lu, Q | en_US |
dc.creator | Sham, CW | en_US |
dc.creator | Lau, FCM | en_US |
dc.date.accessioned | 2017-05-22T02:15:47Z | - |
dc.date.available | 2017-05-22T02:15:47Z | - |
dc.identifier.isbn | 9781509015702 | en_US |
dc.identifier.uri | http://hdl.handle.net/10397/66265 | - |
dc.description | 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016, South Korea, 25-28 October 2016 | en_US |
dc.language.iso | en | en_US |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | en_US |
dc.rights | © 2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. | en_US |
dc.rights | The following publication Q. Lu, C. Sham and F. C. M. Lau, "On using the cyclically-coupled QC-LDPC codes in future SSDs," 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2016, pp. 625-628 is available at https://dx.doi.org/10.1109/APCCAS.2016.7804048. | en_US |
dc.title | On using the cyclically-coupled QC-LDPC codes in future SSDs | en_US |
dc.type | Conference Paper | en_US |
dc.identifier.spage | 625 | en_US |
dc.identifier.epage | 628 | en_US |
dc.identifier.doi | 10.1109/APCCAS.2016.7804048 | en_US |
dcterms.abstract | As the flash memory continues its capacity scaling and correspondingly decreases its reliability, a technology upgrade regarding the error-correction engine in state-of-art solid-state drives (SSDs) is intensely expected. Due to their limit-approaching decoding ability, low-density parity-check (LDPC) codes are seen as one of the most promising substitute for the traditional BCH codes, though implementation barriers remain to degrade their performance. In our recent work, a co-design of LDPC block codes and their decoder architecture are developed and found suitable to apply to address these barriers with an overall excellence in error rate, complexity as well as throughput. Four codes of 4 KB and 4/5 rate are proposed and their FPGA-based implementations are conducted. It is shown that the decoders reach 1.47 Gb/s throughput at 100 MHz clock rates, and their complexity are estimated to be 1 million gates with 1 Mb memory. | en_US |
dcterms.accessRights | open access | en_US |
dcterms.bibliographicCitation | 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016, 25-28 Oct. 2016, 7804048, p. 625-628 | en_US |
dcterms.issued | 2016 | - |
dc.identifier.isi | WOS:000392651200166 | - |
dc.identifier.scopus | 2-s2.0-85011105947 | - |
dc.identifier.ros | 2016005373 | - |
dc.relation.ispartofbook | 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016 | en_US |
dc.relation.conference | IEEE Asia Pacific Conference on Circuits and Systems [APCCAS] | en_US |
dc.source.type | Proceedings Paper | - |
dc.identifier.artn | 7804048 | en_US |
dc.identifier.rosgroupid | 2016005122 | - |
dc.description.ros | 2016-2017 > Academic research: refereed > Refereed conference paper | en_US |
dc.description.validate | 201803_a bcwh | en_US |
dc.description.oa | Accepted Manuscript | en_US |
dc.identifier.FolderNumber | a0721-n20 | - |
dc.description.fundingSource | RGC | en_US |
dc.description.fundingText | RGC: 15208815E | en_US |
dc.description.pubStatus | Published | en_US |
Appears in Collections: | Conference Paper |
Files in This Item:
File | Description | Size | Format | |
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a0721-n20_2016APCCS.pdf | Pre-Published version | 254.69 kB | Adobe PDF | View/Open |
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