Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/66181
Title: Optimization of behavioral IPs in multi-processor system-on-chips
Authors: Liu, Y
Schafer, BC
Issue Date: 2016
Publisher: Institute of Electrical and Electronics Engineers Inc.
Source: Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 2016, v. 25-28-January-2016, 7428034, p. 336-341 How to cite?
Abstract: This work shows that behavioral IPs (BIPs) are often over-designed when used in heterogenous Multi-Procesosr SoCs (MPSoCs) mainly because they are designed and optimized separately. When instantiated in an MPSoC, these IPs often haven to wait for data from the master and also wait to gain access to the bus to return the results. Behavioral IPs have the advantage over traditional RTL-based IPs that they can be re-synthesized with different constraints, which allows the generation of micro-architectures with unique area vs. performance trade-offs. This work leverages this and introduces a method to automatically identify the workload of each behavioral IP mapped as a slave on an MPSoC system and re-synthesizes it to maximize its efficiency, i.e. reduce its area and minimize its idle time, without affecting the overall performance. We show the area can be reduced by up to 26.1% compared to the fastest implementation without any performance degradation and on average by 13.21%. Compared to an exhaustive search our method is only on average 5% worse while on average 16× faster.
Description: 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016, Macau, 25-28 January 2016
URI: http://hdl.handle.net/10397/66181
ISBN: 9781467395694
DOI: 10.1109/ASPDAC.2016.7428034
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