Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/65330
Title: Low ON-resistance SiC Trench/Planar MOSFET with reduced OFF-state oxide field and low gate charges
Authors: Wei, J
Zhang, M
Jiang, H
Cheng, CH 
Chen, KJ
Keywords: Channel density
Feedback capacitance
Gate charge
Oxide protection
SiC trench/planar MOSFET
TP-MOS
Issue Date: 2016
Publisher: Institute of Electrical and Electronics Engineers
Source: IEEE electron device letters, 2016, v. 37, no. 11, p. 1458-1461 How to cite?
Journal: IEEE electron device letters 
Abstract: We propose a SiC trench/planar MOSFET (TP-MOS) which features a trench channel and a planar channel in one half-cell. Numerical simulations with Sentaurus TCAD have been carried out to study the proposed device architecture. Compared with traditional planar MOSFET (P-MOS), the TP-MOS has a much lower RON owing to the increased channel density. Unlike traditional trench MOSFET (T-MOS) which enables a higher channel density at the price of a high bottom-oxide field in the high-voltage OFF-state, the TP-MOS features bottom p-bases as in the P-MOS that protect the gate oxide from high electric field. The OFF-state oxide field in the TP-MOS is found to be even lower than the P-MOS. In addition, the TP-MOS boasts a low feedback capacitance (Crss) and gate-to-drain charge (QGD), since the coupling between the gate and the drain is suppressed by the collective effects of the top p-bases and the bottom p-bases. The QG of the TP-MOS is nearly the same as the P-MOS, and is much smaller than the T-MOS. Superior figures of merits (QG × RON and QGD × RON) are achieved in the TP-MOS.
URI: http://hdl.handle.net/10397/65330
ISSN: 0741-3106
DOI: 10.1109/LED.2016.2609599
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