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Title: Tunable multiprocess mapping on coarse-grain reconfigurable architectures with dynamic frequency control
Authors: Carrion Schafer, B 
Keywords: Adaptive clock
Coarse grained reconfigurable architecture (CGRA)
Dynamic frequency control (DFC)
High-level synthesis
Runtime reconfiguration
Issue Date: 2016
Publisher: Institute of Electrical and Electronics Engineers
Source: IEEE transactions on very large scale integration (VLSI) systems, 2016, v. 24, no. 1, p. 324-328 How to cite?
Journal: IEEE transactions on very large scale integration (VLSI) systems 
Abstract: This brief presents a method to map multiple concurrently executing independent tasks onto a coarse-grain reconfigurable architecture (CGRA) with adaptive frequency control to increase the overall throughput and minimize the total area. The commercial CGRA targeted in this brief is embedded as an IP into reconfigurable systems-on-a-chip and is runtime reconfigurable. It is able to reconfigure its tiles every clock cycle by loading new contexts while adapting its clock. Each tile on the CGRA is composed of a certain number of processing elements and has its own adaptive clock domain. This clock is fully adaptive so that it can match the critical path in each context and hence maximize the throughput. The method proposed in this brief effectively maps multiple independent tasks (applications) onto the same tile(s) in order to minimize the total tiles usage, requiring a smaller CGRA IP area, while achieving high throughput. Experimental results show that our method is very effective and that it can reduce the number of tiles used on average by 31.8% while degrading the overall performance by only 5.7% on average compared with the fastest solution which maps each kernel onto its own tiles with its own adaptive clock.
ISSN: 1063-8210
EISSN: 1557-9999
DOI: 10.1109/TVLSI.2015.2397031
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