Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/54862
Title: Acceleration of the descrete element method : from RTL to C-Based design
Authors: Carrion Schafer, B 
Wakabayashi, K
Issue Date: 2013
Publisher: Springer
Source: In W Vanderbauwhede & K Benkrid (Eds.), High-performance computing using FPGAs, p. 665-693. New York: Springer, 2013 How to cite?
Abstract: Field programmable gate arrays (FPGAs) have been extensively used to accelerate numerical intensive applications as they provide an excellent platform to exploit low- and high-level parallelism. Most of these computational intensive applications are given in high level languages, e.g. C or C++. A direct path from these descriptions to RTL is therefore highly desirable. Many attempts have been made to provide this direct synthesis path. Many years ago we implemented a multi-FPGA scalable custom hardware architectures to accelerate the discrete element method (DEM) in VHDL (Schafer et al. Comput. Struct. 82(20–21), 1707–1718, 2004) and also tried to use high level synthesis (HLS) tools available at that time, unsuccessfully due to their limitations and bad quality of results (QoR). We have re-implemented this custom hardware architecture in C using a state-of-the-art HLS tool and show in this chapter that it is now possible to design and verify entire systems in C achieving comparable QoR to hand-coded RTL. A step by step guide of how to create C-based FPGA designs with results comparable to that of the original hand-coded RTL architecture is presented as well as different benefits that come along behavioural synthesis, including design turn around time (TAT) reduction, design space exploration and high-speed cycle-accurate model generators for full chip verification.
URI: http://hdl.handle.net/10397/54862
ISBN: 1461417910 (electronic bk.)
9781461417910 (electronic bk.)
9781461417903 (print)
DOI: 10.1007/978-1-4614-1791-0_22
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