Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/50487
DC FieldValueLanguage
dc.contributorDepartment of Electronic and Information Engineering-
dc.creatorLu, JW-
dc.creatorChow, WK-
dc.creatorSham, CW-
dc.date.accessioned2016-06-08T01:56:58Z-
dc.date.available2016-06-08T01:56:58Z-
dc.identifier.urihttp://hdl.handle.net/10397/50487-
dc.language.isoenen_US
dc.titleClock network synthesis with concurrent gate insertionen_US
dc.typeConference Paperen_US
dc.identifier.spage228-
dc.identifier.epage237-
dcterms.bibliographicCitationProceedings of the International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS' 2010), Grenoble, France, September 2010, p. 228-237-
dcterms.issued2010-
dc.relation.conferenceInternational Workshop on Power and Timing Modeling, Optimization and Simulation-
dc.identifier.rosgroupidr51556-
dc.description.ros2010-2011 > Academic research: refereed > Refereed conference paper-
Appears in Collections:Conference Paper
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