Please use this identifier to cite or link to this item:
Title: Clock network synthesis with concurrent gate insertion
Authors: Lu, JW
Chow, WK
Sham, CW
Issue Date: 2010
Source: Proceedings of the International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS' 2010), Grenoble, France, September 2010, p. 228-237 How to cite?
Appears in Collections:Conference Paper

Show full item record

Page view(s)

Last Week
Last month
Citations as of Mar 18, 2018

Google ScholarTM


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.