Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/50487
Title: Clock network synthesis with concurrent gate insertion
Authors: Lu, JW
Chow, WK
Sham, CW
Issue Date: 2010
Source: Proceedings of the International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS' 2010), Grenoble, France, September 2010, p. 228-237
Appears in Collections:Conference Paper

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