Please use this identifier to cite or link to this item:
Title: Built-in self-test technique based on weighted sum of selected node voltages
Authors: Ko, KY
Wong, MWT
Lee, YS
Issue Date: 2001
Source: Proceedings of the 9th International Symposium on Integrated Circuits, Devices and Systems (ISIC' 2001), Singapore, September 2001, p. 186-189 How to cite?
Appears in Collections:Conference Paper

Show full item record

Page view(s)

Last Week
Last month
Citations as of Mar 18, 2018

Google ScholarTM


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.