Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/48409
Title: Built-in self-test technique based on weighted sum of selected node voltages
Authors: Ko, KY
Wong, MWT
Lee, YS
Issue Date: 2001
Source: Proceedings of the 9th International Symposium on Integrated Circuits, Devices and Systems (ISIC' 2001), Singapore, September 2001, p. 186-189 How to cite?
URI: http://hdl.handle.net/10397/48409
Appears in Collections:Conference Paper

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