Please use this identifier to cite or link to this item:
Title: FTL2 : a hybrid flash translation layer with logging for write reduction in flash memory
Authors: Wang, T
Liu, DUO
Wang, YI
Shao, Z 
Issue Date: 2013
Source: LCTES '13 Proceedings of the 14th ACM SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems, Seattle, Washington, USA, June 20-21, 2013, p. 91-100
Abstract: NAND flash memory has been widely used to build embedded devices such as smartphones and solid state drives (SSD) because of its high performance, low power consumption, great shock resistance and small form factor. However, its lifetime and performance are greatly constrained by partial page updates, which will lead to early depletion of free pages and frequent garbage collections. On the one hand, partial page updates are prevalent as a large portion of I/O does not modify file contents drastically. On the other hand, general-purpose cache usually does not specifically consider and eliminate duplicated contents, despite its popularity.
Keywords: Caching
Flash memory
Flash translation layer
Partial page update
Solid state drives
ISBN: 978-1-4503-2085-6
DOI: 10.1145/2465554.2465563
Appears in Collections:Conference Paper

View full-text via PolyU eLinks SFX Query
Show full item record


Last Week
Last month
Citations as of Aug 18, 2020

Page view(s)

Last Week
Last month
Citations as of Sep 27, 2020

Google ScholarTM



Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.