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|Title:||Built-in self-test devices and structures for mixed signal integrated circuits||Authors:||Zhang, Yubin||Keywords:||Hong Kong Polytechnic University -- Dissertations
Signal processing -- Digital techniques
Integrated circuits -- Testing
|Issue Date:||2006||Publisher:||The Hong Kong Polytechnic University||Abstract:||In Integrated Circuits (1C) industry, circuit testing consumes a substantially large portion of the total product cost and design time. IC testing is becoming more significant as the complexity and the integration of current circuits are rising. This is due to the high demand of smaller feature scale of the integrated circuits, being shrunk further down into deep sub-micron (DSM) domain nowadays, and at the same time the complex functions on IC chips that have been going up in an order of magnitude. By designing additional circuits on the IC chip for testing purpose besides those normal logic circuits, the built-in circuits and the corresponding test architectures can make it easier to detect circuit faults and therefore the product design time and cost can be greatly reduced. In addition, test strategies are also required to further reduce testing cost. For example, test pattern generation and test response analysis can be integrated with data compaction algorithm to reduce test data volume and thus reduce test time and cost. In this thesis, the proposed design of full range window comparator (FRWC) is presented which can be used effectively in IC testing. Such assistant circuits as self test circuit and decision circuit have also been designed to make the FRWC more reliable and accurate. Detailed analysis and simulation have been conducted to show the effectiveness and characteristics of the proposed FRWC design.
A new Built-in Self-Test (BIST) scheme is proposed in the following of this thesis while this test scheme is based on scan chain structure with the incorporation of the full range window comparator. A number of supporting devices, functional blocks and strategies required in this BIST scheme are also presented in this thesis, such as the core selecting mechanism and the test interface in each core of the System On Chip (SOC). Simulation and analysis of this BIST scheme have also been completed and the details are described in the subsequent chapters of this thesis. A rail to rail voltage comparator design is represented in the later part of this thesis. The design is based on the BSIM4 50nm CMOS transistor model with power supply of 0-1V. This voltage comparator works with high voltage gain and short delay time. Simulation shows that this voltage comparator can maintain good characteristics even when the input voltages are very close to the rail voltages (power supply voltages). Especially, its transient delay time can maintain short in all testing conditions, which is much better than that of the reference comparators. Detailed analysis and characteristic of this design is described in this thesis. Finally, a data compaction method is proposed in chapter 6 of this thesis for compressing interconnects signal integrity test pattern. The proposed method not only can reduce the number of test patterns but also can reduce the length of test patterns (the number of bits in a test pattern) so that the total test data volume can be substantially reduced and this in turn proves that the proposed method can substantially reduce the testing time compared with the original uncompacted test patterns.
|Description:||xiv, 154 leaves : ill. ; 31 cm.
PolyU Library Call No.: [THS] LG51 .H577M EIE 2006 Zhang
|URI:||http://hdl.handle.net/10397/3887||Rights:||All rights reserved.|
|Appears in Collections:||Thesis|
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