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|Title:||Static D.C. fault diagnosis||Authors:||Worsman, Matthew Taylor||Keywords:||Hong Kong Polytechnic University -- Dissertations
Electronic circuit design
Linear integrated circuits -- Testing
Digital integrated circuits -- Testing
|Issue Date:||2003||Publisher:||The Hong Kong Polytechnic University||Abstract:||Testing constitutes a major cost in the design and production of an electronic circuit. The test cost is usually dominated by the cost of testing the analog circuitry. Effective analog circuit test methods are consequently essential to product competitiveness. During the design cycle, testing is performed to characterise a circuit prior to mass production. If a circuit fails specifications, it is often desirable to diagnose the fault so that the circuit can be redesigned to be less sensitive to common failure mechanisms. A faulty parameter is diagnosable if detected, isolated from all other faults and its value calculated. A set of faults that are detectable, but not diagnosable due to similarities in their test response, are termed equivalent. Equivalent faults are an impediment to effective fault diagnosis. Presented is a study of fault equivalence in d.c. steady-state linear analog circuits aiming to characterise, extract and evaluate fault equivalence so as to develop systematic methods for enhancing fault diagnosis.
The characterisation, extraction and evaluation of fault equivalence relationships is a process we term equivalent fault analysis. Characterisation focuses on equivalent faults isolating the output node or resulting in identical one-port network driving-point and/or transfer characteristics. Fault equivalence relationships based on these conditions are shown to prevent effective fault diagnosis in a number of basic linear analog subcircuits, independent of the system in which the analog subcircuits are embedded. Fault equivalence relationships are extracted using cutset analysis and network transformation theory. These methods are demonstrated to provide insight into equivalent fault behaviour not necessarily observable using the traditional system of equations approach. Equivalent fault extraction is simplified by assuming ideal conditions. The validity of this assumption is then verified by evaluating fault equivalence in the presence of non-ideal effects, such as parameter variations, using a set of suggested statistical testability measures that are simple and effective. The uses of equivalent fault analysis in test solution design are demonstrated with 1) the redesign of a potentiometric Digital-to-Analog Converter Built-In Self-Test scheme for improved diagnosis of passive component catastrophic faults, 2) the development of a Design-for-Testability scheme improving the diagnosis of passive component parametric faults in a Wheatstone bridge and amplifier, and the 3) adjustment of component values to improve the testability of a particular component in a Resistance-Temperature-Detector sensor circuit. Hardware and hardware-free test solutions are considered, with results strongly suggesting the former to be the most effective approach for diagnosing equivalent faults. Constraints limiting both test solution types are identified and a methodology for test solution design developed. Results did, however, identify the very limited size of the analysable circuit as the major disadvantage of the proposed equivalent fault analysis. Possible solutions to lessen this problem are suggested.
|Description:||xiv, 135 leaves : ill. ; 30 cm.
PolyU Library Call No.: [THS] LG51 .H577M EIE 2003 Worsman
|URI:||http://hdl.handle.net/10397/3871||Rights:||All rights reserved.|
|Appears in Collections:||Thesis|
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Citations as of Sep 18, 2018
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