Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/37699
Title: DPA : a data pattern aware error prevention technique for NAND flash lifetime extension
Authors: Guo, J
Chen, Z
Wang, D
Shao, Z 
Chen, Y
Keywords: NAND circuits
Error statistics
Flash memories
Issue Date: 2014
Source: 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC 2014) : Singapore, 20-23 January 2014, p. 592-597 How to cite?
Abstract: The recent research reveals that the bit error rate of a NAND flash cell is highly dependent on the stored data patterns. In this work, we propose Data Pattern Aware (DPA) error protection technique to extend the lifespan of NAND flash based storage systems (NFSS). DPA manipulates the ratio of 1's and 0's in the stored data to minimize occurrence of the data patterns which are susceptible to bit error noise. Consequently, the NAND flash cell bit error rate is reduced, leading to system endurance extension. Our simulation result shows that, with marginal hardware and power overhead, DPA scheme can increase the NFSS lifetime by up to 4×, offering a complementing solution to other lifetime enhancement techniques like wear-leveling.
URI: http://hdl.handle.net/10397/37699
DOI: 10.1109/ASPDAC.2014.6742955
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