Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/35928
Title: A reliability enhanced address mapping strategy for three-dimensional (3-D) NAND flash memory
Authors: Wang, Y
Shao, ZL 
Chan, HCB 
Bathen, LAD
Dutt, ND
Keywords: 3-D integrated circuits
Data storage systems
Error correction codes
Fault tolerance
Flash memories
Reliability
Issue Date: 2014
Publisher: Institute of Electrical and Electronics Engineers
Source: IEEE transactions on very large scale integration (VLSI) systems, 2014, v. 22, no. 11, p. 2402-2410 How to cite?
Journal: IEEE transactions on very large scale integration (VLSI) systems 
Abstract: The linear scaling down of NAND flash memory is approaching its physical, electrical, and reliability limitations. To maintain the current trend of increasing bit density and reducing bit per cost, 3-D flash memory is emerging as a viable solution to fulfill the ever-increasing demands of storage capacity. In 3-D NAND flash memory, multiple layers are stacked to provide ultrahigh density storage devices. However, the physical architecture of 3-D flash memory leads to a higher probability of disturbance to adjacent physical pages and greatly increases bit error rates. This paper presents a novel physical-location-aware address mapping strategy for 3-D NAND flash memory. It permutes the physical mapping of pages and maximizes the distance between the consecutively logical pages, which can significantly reduce the disturbance to adjacent physical pages and effectively enhance the reliability. The proposed mapping strategy is applied to a representative flash storage system. Experimental results show that the proposed scheme can reduce uncorrectable page errors by 70.16% with less than 10.01% space overhead in comparison with the baseline scheme.
URI: http://hdl.handle.net/10397/35928
ISSN: 1063-8210 (print)
1557-9999 (online)
DOI: 10.1109/TVLSI.2013.2288687
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