Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/35506
Title: S2CBench : synthesizable systemc benchmark suite for high-level synthesis
Authors: Schafer, BC 
Mahapatra, A
Keywords: Benchmark testing
Design automation
High level synthesis
Issue Date: 2014
Publisher: Institute of Electrical and Electronics Engineers
Source: IEEE embedded systems letters, 2014, v. 6, no. 3, 3, p. 53-56 How to cite?
Journal: IEEE embedded systems letters 
Abstract: High-level synthesis (HLS) is being increasingly used for commercial VLSI designs. This has led to the proliferation of many HLS tools. In order to evaluate their performance and functionalities, a standard benchmark suite in a common language supported by all of them is required. This letter presents a benchmark suite, which complies with the latest Synthesizable SystemC standard, called S2CBench. The benchmarks have been carefully chosen to not only include applications of different sizes and from various domains typically used in HLS (e.g., encryption, image and DSP application), but also to test specific optimization techniques in each of them. This allows an easy comparison of not only quality of results (QoR) of the different HLS tools under review, but also to test their completeness.
URI: http://hdl.handle.net/10397/35506
ISSN: 1943-0663 (print)
1943-0671 (online)
DOI: 10.1109/LES.2014.2320556
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