Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/34411
Title: Loop scheduling with timing and switching-activity minimization for VLIW DSP
Authors: Shao, Z 
Xiao, B 
Xue, C
Zhuge, Q
Sha, EHM
Keywords: VLIW
Compilers
Loops
Software pipelining
Retiming
Instruction bus optimization
Low-power optimization
Instruction scheduling
Issue Date: 2006
Publisher: Association for Computing Machinery
Source: ACM transactions on design automation of electronic systems, 2006, v. 11, no. 1, p. 165-185 How to cite?
Journal: ACM transactions on design automation of electronic systems
Abstract: In embedded systems, high-performance DSP needs to be performed not only with high-data throughput but also with low-power consumption. This article develops an instruction-level loop-scheduling technique to reduce both execution time and bus-switching activities for applications with loops on VLIW architectures. We propose an algorithm, SAMLS (Switching-Activity Minimization Loop Scheduling), to minimize both schedule length and switching activities for applications with loops. In the algorithm, we obtain the best schedule from the ones that are generated from an initial schedule by repeatedly rescheduling the nodes with schedule length and switching activities minimization based on rotation scheduling and bipartite matching. The experimental results show that our algorithm can reduce both schedule length and bus-switching activities. Compared with the work of Lee et al. [2003], SAMLS shows an average 11.5% reduction in schedule length and an average 19.4% reduction in bus-switching activities.
URI: http://hdl.handle.net/10397/34411
ISSN: 1084-4309 (print)
1557-7309 (online)
DOI: 10.1145/1124713.1124724
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