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Title: Area reduction by deadspace utilization on interconnect optimized floorplan
Authors: Sham, CW
Young, EF
Keywords: Floorplanning
Area reduction
Issue Date: 2007
Publisher: Association for Computing Machinary
Source: ACM transactions on design automation of electronic systems, 2007, v. 12, no. 1, 3 How to cite?
Journal: ACM transactions on design automation of electronic systems 
Abstract: Interconnect optimization has become the major concern in floorplanning. Many approaches would use simulated annealing (SA) with a cost function composed of a weighted sum of area, wirelength, and interconnect cost. These approaches can reduce the interconnect cost efficiently but the area penalty of the interconnect optimized floorplan is usually quite large. In this article, we propose an approach called deadspace utilization (DSU) to reclaim the unused area of an interconnect optimized floorplan by linear programming. Since modules are not necessarily rectangular in shape in floorplanning, some deadspace can be redistributed to the modules to increase the area occupied by each module. If the area of each module can be expanded by the same ratio, the whole floorplan can be compacted by that ratio to give a smaller floorplan. However, we will limit the compaction ratio to prevent overcongestion. Experiments show that we can apply this deadspace utilization technique to reduce the area and total wirelength of an interconnect optimized floorplan further while the routability can be maintained at the same time.
ISSN: 1084-4309
DOI: 10.1145/1188275.1188278
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