Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/34055
Title: Modelling of multilayer on-chip transformers
Authors: Tsui, C
Tong, KY
Issue Date: 2006
Publisher: Institution Engineering Technology-Iet
Source: IEE proceedings: microwaves, antennas and propagation, 2006, v. 153, no. 5, p. 483-486 How to cite?
Journal: IEE Proceedings: Microwaves, Antennas and Propagation 
Abstract: An analytical model has been proposed for multilayer stacked on-chip transformers, including the effects of the eddy current losses in the metal layers and Si substrate. The model gives good agreement with S-parameter measurements on structures fabricated using a four-metal-layer 0.35μm CMOS process. It is shown that proper account of the eddy current losses is necessary to predict accurately the S-parameter characteristics of on-chip transformers at higher frequencies.
URI: http://hdl.handle.net/10397/34055
ISSN: 1350-2417
DOI: 10.1049/ip-map:20050135
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